ASIC RTL Engineer

Senior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols)In depth knowledge on RTL quality checks (Lint, CDC)Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)Understanding of scripting languages like Make flow, Perl ,shell, python etcAble to help and debug issues for multiple subsystemsWipro Limited...

Senior ASIC/So C RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols)In depth knowledge on RTL quality checks (Lint, CDC)Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)Understanding of scripting languages like Make flow, Perl ,shell, python etcAble to help and debug issues for multiple subsystemsWipro Limited...

ASIC RTL Design Engineer Location : Bangalore Job Description: Skills & Experience: • 3-5 years of experience in ASIC front end design and quality check. • Strong fundamental knowledge of digital design, Verilog, and scripting language. • Experience in multiple clock and voltage domain design. • Working knowledge for FE flows like Lint, CDC,...

ASIC RTL Design Engineer Location : Bangalore Job Description: Skills & Experience: • 3-5 years of experience in ASIC front end design and quality check. • Strong fundamental knowledge of digital design, Verilog, and scripting language. • Experience in multiple clock and voltage domain design. • Working knowledge for FE flows like Lint, CDC,...

😊Greetings of the day😊!!! This is regarding a Job opportunity with eInfochips as we are having a position of ASIC RTL DESIGN ENGINEERS Experience- 5+ Years Location- Bangalore, Ahmedabad Job Description: Experience in RTL design Verilog/VHDL Simulation tools, Modeslim/VCS etc. Basic protocols, I2C, UART, PCIe, SPI etc. Micro-Architecture experience is...

😊Greetings of the day😊!!! This is regarding a Job opportunity with eInfochips as we are having a position of ASIC RTL DESIGN ENGINEERS Experience- 5+ Years Location- Bangalore, Ahmedabad Job Description: Experience in RTL design Verilog/VHDL Simulation tools, Modeslim/VCS etc. Basic protocols, I2C, UART, PCIe, SPI etc. Micro-Architecture experience is...

Senior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols)Exp - 4 - 20Location :Bengaluru, Hyderabad, Pune, Noida, KochiExpertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System VerilogIn depth knowledge on RTL quality checks (Lint, CDC)Knowledge...

Key skills with hand on: ASIC,RTL Design, VLSI-SOC ,AMBA, Lint, CDC, Synopsys LintCDC/VerdiXcellium/Synopsys DC.Experience: 5 - 25 yearsWork Location: Trivandrum, Bangalore, Hyderabad, Chennai, PuneEducation: Engineering (excluding Mechanical/Civil)Detailed JD:IP RTL design targeted for SOC, Static checks, some basic protocolsExpertise in SoC subsystem/IP...

ASIC RTL Design Engineer Location : Bangalore Job Description: Skills & Experience: • 3-5 years of experience in ASIC front end design and quality check. • Strong fundamental knowledge of digital design, Verilog, and scripting language. • Experience in multiple clock and voltage domain design. • Working knowledge for FE flows like Lint, CDC,...

RTL Design: Design and implement RTL code for ASICs in Verilog or SystemVerilog. Create high-quality, reusable, and maintainable RTL code for complex digital systems.Architecture Design: Work closely with architects to understand the high-level design specifications and translate them into efficient RTL code. Participate in defining micro-architecture for...