ASIC SOC RTL Design Architect
1 week ago
Hi All,Eximietas Design Hiring Senior RTL Design ( Micro-architecture ) Architects / Sr. Manager.Experience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.❖ Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics.❖ Engineering 10+ years of ASIC SOC RTL ( Micro-architecture ) experience.❖ ARM Processor Integration Preferably M55 is a Must.❖ Strong understanding of design concepts.❖ ASIC flow Understanding of SDC Understanding STA reports.❖ Understanding of CDC logic Knowledge of lint rules and exceptions.❖ Design and use of block level simulations to bring up IP.❖ Knowledge of AMBA buses and when to use them.❖ Knowledge on common processor architectures (ARM, RiscV).❖ FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA.❖ Relevant tool experience such as: Socrates, Core Consultant in addition to standard simulation tools (xcellium, vcs, etc) JTAG debugging experience (Coresight, Lauterbach, etc).❖ Low power design techniques / UPF As an RTL Engineer, Candidate will be responsible to work at IP, Subsystem, or SoC-related tasks.Responsibilities:❖ Collaborate with architects, pre- and post-silicon verification teams to meet deadlines.❖ Coordinate with customer leads, ensuring all deliverables and timelines are met.If this opportunity interests you—or if you know someone suitable—please send your updated resume to: are highly appreciated.Best regards,Maruthy PrasaadAssociate VLSI Manager - Talent Acquisition | VisakhapatnamEximietas .
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Innovative RTL Design Expert
2 weeks ago
pune, India beBeeDesigner Full timeJob DescriptionDesign and integrate complex SoCs, leveraging expertise in Logic design/RTL coding and SoC design integration.Utilize Verilog/System-Verilog to drive innovation and excellence in the field of RTL Design Engineering.Required Skills and QualificationsExpertise in multi-clock designs, asynchronous interfaces, and ASIC development tools like Lint...
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SoC RTL Designer
4 weeks ago
Pune, India Lattice Semiconductor Full timeOverview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing,...
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SoC RTL Designer
1 week ago
Pune, Maharashtra, India Lattice Semiconductor Full time US$ 1,20,000 - US$ 2,40,000 per yearLattice OverviewThere is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales,...
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SoC RTL Designer
2 weeks ago
| IN-MH-Pune Lattice Semiconductor Full time US$ 8,00,000 - US$ 10,00,000 per yearLattice OverviewThere is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales,...
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Staff SoC RTL Designer
4 weeks ago
Pune, India Lattice Semiconductor Full timeOverview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing,...
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Staff Soc Rtl Designer
2 days ago
Pune, Maharashtra, India Lattice Semiconductor Full timeLattice Overview There is energy here energy you can feel crackling at any of our international locations It s an energy generated by enthusiasm for our work for our teams for our results and for our customers Lattice is a worldwide community of engineers designers and manufacturing operations specialists in partnership with world-class sales marketing and...
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RTL Design Engineer
3 days ago
pune, India The Machine Learning Company Full timeJob Description - RTL / Verilog Design Engineer (TMLC) About The Machine Learning Company (TMLC) TMLC is a deep-tech engineering company that builds advanced AI and automation systems for global enterprises. Our culture is built on technical rigor, clarity of thought, and product-driven execution. We work at the intersection of ML, systems engineering, and...
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Strategic DFT Architect
4 days ago
pune, India beBeeDft Full timeJob Title: Strategic DFT ArchitectAs a seasoned DFT expert, you will be responsible for leading the design and implementation of digital testability architectures across complex SoC/ASIC designs.Develop and drive DFT strategy and architecture for multiple ASIC/SoC projects, ensuring optimal testability and manufacturability.Oversee the implementation and...
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RTL Design Engineer
4 days ago
pune, India The Machine Learning Company Full timeJob Description - RTL / Verilog Design Engineer (TMLC)About The Machine Learning Company (TMLC)TMLC is a deep-tech engineering company that builds advanced AI and automation systems for global enterprises. Our culture is built on technical rigor, clarity of thought, and product-driven execution. We work at the intersection of ML, systems engineering, and...
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Senior Physical Design Engineer 7-10years
2 weeks ago
Pune, Maharashtra, India Massivetronics Private Limited Full timeCompany DescriptionMassivetronics is a startup based out of Bengaluru, specializing in diverse platforms including ASIC Design, SOC, IOT, AI Robotics, and Telecom. Guided by industry experts, the company is dedicated to innovation and technological development. Massivetronics offers opportunities for professionals to work on cutting-edge projects in a...
