Fpga engineer

Develop RTL code to implement FPGA-based digital designs, working from specification stage through to system integration. Projects will range from Mid to Complex Design. Projects include designing logic for widely used generation of high speed serial protocols, and control logic (bus interfaces and state machines).
Understand the customer requirements and product definition
Define architecture and detailed design specification based on requirements and various trade-offs
Micro-architecture and coding of assigned module in VHDL/Verilog
Write test bench for verifying design for complete scenario coverage
Implement block level RTL, perform synthesis and achieve timing closure.
Implementation of the integrated design on FPGA after required optimization based on available resources and timing closure requirement
FPGA debugging and HW/SW integration
Work with cross-functional teams (hardware, software, and diagnostics).
Requirements :
2+ years of experience, including successful completion of FPGA based projects
Proficiency in HDL languages (Verilog, VHDL and System Verilog)
Experienced in designing with Xilinx, Altera and Microsemi FPGAs
Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus etc. is required
Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor
Implementation of designs with multiple clock domains is required
Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for area and speed
Experience in RTL implementation
Experience in interfaces like PCIe, Ethernet, transceivers, DDR, ADC, DAC, AMBA-AXI, SRAM, USB, UART, I2 C, SPI, memory controllers, UART etc. will be preferred
Education
UG: Electronics
PG: Electronics
Key Skills
RTL design
VHDL
Verilog
System Verilog
UVM
FPGA
System integration
Debugging

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