
RTL Design Engineer
1 day ago
Job Responsibility:
- Drive architecture definition in conjunction with the Systems Architects, and working with the cross function Design, Verification, Validation and supporting SW/FW teams.
- Own the complete design of one or more cutting edge digital IPs from specification to final design delivery
- Deliver IP with first time right quality, ensuring best in class KPIs and performance
- Contribute to continuous methodology developments to improve the speed and reliability of IP execution, and the critical KPIs
- Ensure proper documentation of IP design specifications, and release checks
Job Qualification:
- BSEE required, MSEE preferred with 7+ years of industry related experience
- Must have experience in ASIC/SoC front-end (preferably RTL Verilog and VHDL based) design and methodologies
- Self-driven and capable for independent work and independent decision making.
- Fluency in design & verification languages such as VHDL, Verilog, C and System Verilog.
- Knowledge on Verification Methodologies to actively participate in Debug Analysis
- Prior experience in developing foundation IPs and differentiating/market-oriented IPs
- Excellent written and verbal communication skill.
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