Senior Design Verification Engineer
1 month ago
Projects span a variety of business lines, and designs will need to meet a wide range of power/performance/area goals, depending on the product. Engagement and collaboration across global sites is a key aspect of this role as alignment of methods is essential and sharing of resources is common. Solid technical, communication, and consensus-building skills and the ability to influence solutions across a global organization will be required.
Contribute to the Verification R&D team that is driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors.
Work closely with system architects and support define high level specifications that are implementable and robust.
Interface with verification/validation teams to ensure design quality and robustness.
Practice strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones
Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips
Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies
Contribute to driving best-in-class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI
Participate in customer engagements assessing quality and risks
Qualifications:
Degree in Electrical Engineering or Computer Science, with 5+ years of experience in IP/Sub-System Verification.
Experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
Experience in Microcontroller and Microprocessor architecture, Interconnect, and Cache Coherency.
Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers.
Good knowledge of Verilog, System Verilog, C/C++, and Shell.
Good knowledge in scripting like Perl, TCL, or Python is a plus
Proficiency in Metric Driven Verification concepts, and functional and code coverage.
Expertise in directed and constrained random methodologies.
Good knowledge of formal verification methodologies and assertions.
Experience with debugging of designs pre- and post-silicon, in simulation, and on the bench.
Excellent written and verbal communication skills.
Experience with System Verilog and front-end tooling (simulation, waveform viewers, lint, CDC, RDC, etc.) is required, as well as highly efficient FE methodologies.
Experience working with complex, multi-core SoC’s with extensive interconnects and a large range of peripherals is preferred.
Domain knowledge of clocking, system modes, power management, debug, security, and other architectures is preferred.
Any of the following experiences would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; and Flash memory subsystems.
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