Immediate Start

2 days ago


Hyderabad, India ACL Digital Full time
Lead Verification Engineer
Experience: 7+ years
Handle regression testing and contribute to verification infrastructure development
Collaborate with design, software and architecture teams to verify design under test

Preferred Experience:
Proficient in Verilog/SystemVerilog, and scripting languages such as Perl or Python
Hands-on experience with SystemVerilog and UVM is mandatory
Experience in developing UVM-based verification testbenches, processes, and flows
ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation.

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