Senior Design Verification Engineer

17 hours ago


India ACL Digital Full time

Senior Design Verification Engineer Experience : 5-10 years Location : Hyderabad Functional Verification Engineer Role Summary: We are seeking an experienced Functional Verification Engineer with strong expertise in SystemVerilog/UVM to develop and maintain verification environments for block-level and IP-level designs. The ideal candidate will be proactive, self-driven, and capable of managing deliverables independently. Key Responsibilities: Develop and maintain block-level testbenches using SystemVerilog/UVM. Create and execute verification plans (Vplan) , run regressions, and achieve coverage closure. Work on testbenches with real number modeling . Perform netlist and gate-level simulations . Qualifications & Experience: Education: Bachelor’s degree or higher in Electronics or related field. Experience: 5–10 years in functional verification. Skills: Hands-on coding in SystemVerilog/UVM . Experience with block/IP-level verification; subsystem or SoC-level experience is a plus. Soft Skills: Strong communication, ability to work independently and meet schedules. Interested,please share your updated resume to



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