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Sr. Design Verification Lead
1 month ago
Job Description: We are seeking an experienced Design Verification Lead with a minimum of 15 years of expertise in the semiconductor domain, specifically in design verification. The ideal candidate will be responsible for developing and debugging test cases in a System Verilog/UVM environment and working closely with the team for coverage closure across various protocols. Job Title: Sr. Design Verification Lead Location: Bangalore, India Experience: 15+ years Key Responsibilities: Develop test cases in a SystemVerilog/UVM environment. Debug failing test cases to identify bugs in both design and verification environments. Collaborate with team members to ensure functional and code coverage closure, including conditional, expression, and branch coverage. Work on verification of key protocols like PCIe, DDR, Ethernet, AMBA, AXI, USB, and CXL. Supervise and act as a technical leader for all Tech-M team members. Mentor and provide guidance to Tech-M teams and assist in debug activities. Apply strong UVM and general verification methodologies (Test Bench Architecture, Gate-level simulations, coverage closure). Leverage C and SystemVerilog DPI interface industrial experience. Qualifications: Proven experience with UVM and strong verification methodologies. Excellent problem-solving and debugging capabilities. Expertise in protocols like PCIe, DDR, Ethernet, AMBA, AXI, USB, CXL. Strong communication and leadership skills, with experience mentoring teams. Industrial experience with C and SystemVerilog DPI interface. Cheers, Shahid
