Lead Engineer
6 days ago
Responsibilities:
Develop and execute verification plans using System Verilog and UVM to validate complex ASIC/FPGA designs.
Design and implement testbenches and verification environments to ensure functional accuracy and performance.
Perform Gate-Level Simulations (GLS) to validate designs against their RTL implementations.
Create and run comprehensive verification scenarios and identify discrepancies between RTL and gate-level simulations.
Verify and debug low-power design
Debug SDF Back Annotated Gate Simulations
Collaborate with cross-functional teams to define and execute gate-level simulation test plans.
Develop and implement gate-level simulation strategies for complex digital designs.
Conduct gate-level simulations to verify the functionality and performance of digital designs.
Work closely with design and verification teams to identify and resolve issues at the gate level.
Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process.
Ensure compliance with industry standards and best practices in gate-level simulation.
Develop a comprehensive GLS methodology for the CPU
Perform gate-level simulations to verify the functionality, performance, and timing of CPU designs.
Develop and execute comprehensive test plans for gate-level simulations.
Collaborate with RTL design, verification, and physical design teams to identify and resolve simulation issues.
Familiarity with static timing analysis (STA) and power analysis.
Understanding of power domains and HW programming guide sequences
Develop test plan to verify all low power states
Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals
Exploring innovative dynamic or static methodologies by engaging with EDA vendors
Experience Level: 6-8 years in Industry
Education Requirements: Bachelor or Master’s degree in Electrical and/or Computer Engineering
Minimum Qualifications:
6+ years of professional experience in ASIC/FPGA verification with strong expertise in SystemVerilog, UVM, and Gate-Level Simulation (GLS).
Proven experience in developing and executing testbenches and verification environments.
Strong skills in performing gate-level simulations and analyzing results.
Verify and debug low-power design
Debug SDF Back Annotated Gate Simulations
Low-power implementation (UPF)
Mixed Signal Real Number Modeling (RNM, Spice)
Strong System Verilog/UVM based verification skills
Experience with Assertion coverage-based verification methodology
Experience in formal / static verification methodologies will be a plus
Good understanding of low power design techniques
Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells.
Experience with UPF/CPF based power aware verification.
Experience with Synopsys NLP (native Low Power) tool.
Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus
Proficiency in Low-Power standards like UPF/CPF.
Working knowledge on UPF based RTL / PGPIN simulations.
Proficiency in ASIC design tools, simulation methodologies, and hardware description languages (HDLs).
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