DV- PCIE Verification Engineer

LTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design...

Job Location: Bangalore/ HyderabadNotice Period: 15 days to 30 DaysMinimum: 4 YearsKey Responsibilities:Developing test plansCoding and bring up of asm, c++ testsUVM test bench components coding and maintainingDebugging regression failsProtocol: DDR,PCIE,USB,MIPI, PCIEPreferred Experience:Should have worked on Processor based System or Sub-system level...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...

Hi All, ACL Digital is hiring Design Verification Engineers Experience: 8+ years Location: Hyderabad / Bangalore Join: Immediate Key Skills: 8+ Years in IP/Sub-System/SoC DV Testbench Development Strong in SV UVM, Functional & Formal Verification Hands-on with RISC-V / CPU / PCIe / DDR / Ethernet SoC Integration, Debugging & Coverage...

ACL Digital Hiring for the below requirementDesignation: DV engineersExperience: 8-10+ yearsLocation: BangaloreJob Description:1. Hands-on experiences on SV/UVM/Specman2. Familiarity with formal-based verification3. Running regression and debugging failures independently4. Experience in functional and code coverages5. Independently handling sub-module-level...

PCIe Verification: Lead the verification of PCIe (PCI Express) interface designs, ensuring compliance with PCIe protocol standards (e.g., PCIe Gen 3/4/5/6, USB3, etc.).Testbench Development: Develop and implement scalable, reusable, and efficient testbenches for PCIe designs using SystemVerilog, UVM (Universal Verification Methodology), and other...

PCIe Verification: Lead the verification of PCIe (PCI Express) interface designs, ensuring compliance with PCIe protocol standards (e.g., PCIe Gen 3/4/5/6, USB3, etc.).Testbench Development: Develop and implement scalable, reusable, and efficient testbenches for PCIe designs using SystemVerilog, UVM (Universal Verification Methodology), and other...

Design Verification Engineer - Senior / Lead / Sr. Lead Location: Bangalore / Hyderabad Experience: 4 to 10 Years Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering , Computer Engineering , or a related field. 4+ years of hands-on experience in design verification of high-speed interfaces such as...

Design Verification Engineer - Senior / Lead / Sr. LeadLocation: Bangalore / HyderabadExperience: 4 to 10 YearsRequired Qualifications:Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.4+ years of hands-on experience in design verification of high-speed interfaces such as DDR, PCIe, UCIe, or NVMe.Expertise...

We’re Hiring | Seniors/Leads/ Managers Design Verification Engineers Are you passionate about IP, Subsystem, and SoC level verification ? Join Mirafra Technologies and be part of an innovative journey in the Semiconductor & VLSI domain , working on cutting-edge projects with a dynamic team! Role: Seniors/Leads/ Managers Design...