Senior Design Verification Engineer

Design Verification Engineer (7-10 years’ experience)Company: HCL TechJob Summary:We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits.Responsibilities:Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification)Design and create high-quality verification environments (testbenches) to achieve exceptional code coverageUtilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionalityDebug and analyze verification failures with a keen eye to identify and resolve the root cause of design issuesCollaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherenceLead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environmentParticipate in code reviews and champion best practices for verification code qualityStay current with the latest advancements in verification tools and methodologiesQualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)7-10 years of solid experience in Design Verification for ASICs or SoCsIn-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)Proven ability to develop, debug, and optimize complex verification environmentsExpertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal)Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl)Experience with formal verification tools and techniques is a plusExcellent analytical and problem-solving skills with a meticulous attention to detailStrong communication, collaboration, and leadership skills to effectively contribute and guide the teamBenefits:Competitive salary and benefits package commensurate with experienceOpportunity to work on leading-edge technologies and projects with a high impactCollaborative and dynamic work environment that fosters continuous learningPotential for professional development and career advancementDesign Verification Engineer (Senior Level - 10+ years’ experience)Company: HCL TechJob Summary:We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies.Responsibilities:Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification)Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goalsUtilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysisDebug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolutionMentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the teamChampion best practices for verification code quality and participate in code reviewsStay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologiesProvide technical leadership and contribute to the overall verification roadmap for the teamQualifications:Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred)Minimum of 10+ years of experience in Design Verification for complex ASICs and SoCsProven track record of successfully leading and executing verification projectsIn-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practicesExpertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniquesExtensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages)Excellent leadership, communication, collaboration, and problem-solving skillsAbility to manage multiple projects, prioritize tasks, and meet aggressive deadlinesBenefits:Competitive salary and benefits package commensurate with experience and expertiseOpportunity to lead and influence the verification of cutting-edge technologiesDynamic and challenging work environment with opportunities for professional growth and leadership developmentRecognition and rewards for outstanding contributions