Design and Analysis Engineer

2 weeks ago

Chennai, India ACL Digital Full time

RTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 1 to 3 Years Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into SoC environments and support design convergence. Collaborate with system architects, verification, SoC, software, DFT, and physical design teams. Apply low-power design techniques including clock gating, power gating, and multi-voltage domains. Analyze and optimize for performance, area, and power. Ensure protocol compliance and performance of interconnects, buses (AXI, AHB, APB), and bridges. 1–3 years of experience in digital front-end ASIC/RTL design. ~ Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. ~ Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic. ~ Experience with wireless modem IPs or similar high-performance digital blocks is a plus. ~ Familiarity with low-power design methodologies and CDC handling. ~ Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. ~ Self-motivated with a collaborative mindset and ability to work with minimal supervision. ACL Digital, part of the ALTEN Group, is a trusted AI-led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack — from chip to cloud. By integrating AI and data-powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes.

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