Memory Circuit Design Engineer

2 days ago

Bangalore, India Capgemini Engineering Full time

Role: Memory Circuit Design Engineer Experience: 5 to 12 Years Location: Bengaluru Job Description: Digital Full Custom CKT Design Bitcell Design Design of simpler memory blocks (decoding, rowdec, SA, IO block w/o RA, WA) Design of complex blocks like RA, WA, Rd selftime and write selftime SPRAM/Dual Port/ROM architecture Exploring and providing new ckt design and memory architectures – Nice to have Library CKT verification at Compiler level Sense Amp Analysis(offset, pulse width, glitch, coupling etc.)" Read/Write Selftime Analysis Functional/Power Marginality analysis Latch analysis ESPCV Power ON and power sequencing checks Extraction, IR/EM analysis, PERC etc. – Nice to have Library CKT Char and Char verification Timing, power, leak etc. setups(definitions, stimuli, MCF etc.) Timing, power, leak etc. verification (new addition) LVF analysis and implementation Critical Path Tight Stimuli (CPTS) Full Cut Tight Stimuli (FCTS) FC power, timing, power, leak and comparison with CP Decoupling CAP Ageing (char) Concept of Grid – Concept should be known; methodology can be different in diff organizations Infrastructure, Packaging & Delivery – ST Methodology will be trained separately CAD Tools (More conceptual knowledge needed, tools can be different) Global BIST solutions e.g., MASIS, IR Drop solutions, AVM, RedHawk etc. Simulators e.g., XA, Eldo High sigma analysis (eldo FFP etc.)

  • Memory Circuit Design Engineer

    1 day ago

    bangalore district, India Capgemini Engineering Full time

    Role: Memory Circuit Design Engineer Experience: 5 to 12 Years Location: Bengaluru Job Description: Digital Full Custom CKT Design Bitcell Design Design of simpler memory blocks (decoding, rowdec, SA, IO block w/o RA, WA) Design of complex blocks like RA, WA, Rd selftime and write selftime SPRAM/Dual Port/ROM architecture Exploring and providing new ckt...

  • Memory Design Engineers

    4 days ago

    Bangalore, India ACL Digital Full time

    Job Title: Memory Design Engineer Experience Required: 2+ Years Location: Bangalore Job Type: Full-time Industry: Semiconductors / VLSI / Memory IP Job Summary: We are seeking a skilled Memory Design Engineer to join our advanced memory IP development team. The candidate will be responsible for architecting, designing, and validating high-performance and...

  • Memory Circuit Design Engineer

    3 days ago

    bangalore, India Capgemini Engineering Full time

    Role: Memory Circuit Design EngineerExperience: 5 to 12 YearsLocation: BengaluruJob Description:Digital Full Custom CKT DesignBitcell DesignDesign of simpler memory blocks (decoding, rowdec, SA, IO block w/o RA, WA)Design of complex blocks like RA, WA, Rd selftime and write selftimeSPRAM/Dual Port/ROM architectureExploring and providing new ckt design and...

  • Lead Memory Design Engineer

    3 weeks ago

    Bangalore, India ACL Digital Full time

    Job Title: Lead Memory Design Engineer Experience: 6+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / VLSI / Memory IP / SoC Job Summary: We are looking for an experienced and highly motivated Lead Memory Design Engineer to drive the architecture, design, and development of advanced memory IPs such as SRAMs, ROMs, CAMs, and...

  • Lead Memory Design Engineer

    2 days ago

    Bangalore, India ACL Digital Full time

    Job Title: Lead Memory Design Engineer Experience: 6+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / VLSI / Memory IP / SoC Job Summary: We are looking for an experienced and highly motivated Lead Memory Design Engineer to drive the architecture, design, and development of advanced memory IPs such as SRAMs, ROMs, CAMs, and...

  • ▷ High Salary: Memory Design Engineer

    3 weeks ago

    Bangalore, India ACL Digital Full time

    Position: Senior Memory Design Engineer Location: Bangalore / Noida Responsibilities: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA. Required Skills and Experience : - Understanding of computer architecture and concepts. - Basic understanding of...

  • Lead Memory Design Engineer

    2 weeks ago

    Bangalore Division, India ACL Digital Full time

    Job Title: Lead Memory Design Engineer Experience: 6+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / VLSI / Memory IP / SoC Job Summary: We are looking for an experienced and highly motivated Lead Memory Design Engineer to drive the architecture, design, and development of advanced memory IPs such as SRAMs, ROMs, CAMs, and...

  • Senior Memory Design Lead Engineer

    1 day ago

    bangalore district, India ACL Digital Full time

    Position: Senior Memory Design Lead Engineer Location: Bangalore Responsibilities: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA. Required Skills and Experience : Understanding of computer architecture and concepts. Basic understanding of CMOS...

  • Senior Memory Design Lead Engineer

    1 day ago

    Bangalore Division, India ACL Digital Full time

    Position: Senior Memory Design Lead Engineer Location: Bangalore Responsibilities: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA. Required Skills and Experience : Understanding of computer architecture and concepts. Basic understanding of CMOS...

  • Senior Memory Design Lead Engineer

    1 day ago

    Bangalore Urban, India ACL Digital Full time

    Position: Senior Memory Design Lead Engineer Location: Bangalore Responsibilities: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA. Required Skills and Experience : Understanding of computer architecture and concepts. Basic understanding of CMOS...