Senior DFX Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry our communities and the world Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center artificial intelligence PCs gaming and embedded Underpinning our...

Job Description: Develop and execute pre-silicon verification test plans for DFT features of the chip. Develop directed and random verification tests to validate the functionality. Verify DFT design blocks and subsystems (such as MBIST, high speed IO PHY, fuse, clocks, reset) using complex SV or C++ verification environments. Construct SystemVerilog...

Job Description:Develop and execute pre-silicon verification test plans for DFT features of the chip. Develop directed and random verification tests to validate the functionality.Verify DFT design blocks and subsystems (such as MBIST, high speed IO PHY, fuse, clocks, reset) using complex SV or C++ verification environments. Construct SystemVerilog and/or...

Senior Verification Engineer - Location: Bangalore/Hyderabad - Experience: 4+ years - 1Must have very good System Verilog/UVM experience - Must have expertise in PCI gen6 and CXL3.1or Ethernet bus protocols - Have experience in IP/SoC Verification - Expertise in AMBA/AXI bus protocols and ARM CPU - Experience in developing functional verification...

Senior Verification EngineerLocation: Bangalore/HyderabadExperience: 4+ years1Must have very good System Verilog/UVM experienceMust have expertise in PCI gen6 and CXL3.1or Ethernet bus protocolsHave experience in IP/SoC VerificationExpertise in AMBA/AXI bus protocols and ARM CPUExperience in developing functional verification environments including the...

POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ Ahmedabad ROLE & RESPONSIBILITIES An expert level with developing UVM-based SV test-benches. Highly experienced with defining block, sub-system and SOC top level test plans. Relevant experience with one or more of PCIe,...

Senior Design Verification Engineer: Should have PCIE IP level verification exposure Good UVM understanding Serial protocol understanding Interested,please drop your updated CV to

Senior Design Verification Engineer: Should have PCIE IP level verification exposure Good UVM understanding Serial protocol understanding Interested,please drop your updated CV to

POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ AhmedabadROLE & RESPONSIBILITIES An expert level with developing UVM-based SV test-benches.Highly experienced with defining block, sub-system and SOC top level test plans.Relevant experience with one or more of PCIe, NVMe, NAND, DDR and...

Senior Design Verification Engineer:Should have PCIE IP level verification exposureGood UVM understandingSerial protocol understandingInterested,please drop your updated CV to janagaradha.n@acldigital.com