Design Verification Engineer

Job OverviewWe are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs.Job DescriptionLead and manage SOC...

Role Overview:We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology . The ideal candidate will have hands-on experience in SoC and IP-level verification across multiple domains, along with good scripting skills. Exposure to C language is a plus.Key Responsibilities:Develop and execute...

Role Overview: We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology . The ideal candidate will have hands-on experience in SoC and IP-level verification across multiple domains, along with good scripting skills. Exposure to C language is a plus. Key Responsibilities: Develop and execute...

Role Overview: We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology . The ideal candidate will have hands-on experience in SoC and IP-level verification across multiple domains, along with good scripting skills. Exposure to C language is a plus. Key Responsibilities: Develop and execute...

Role Overview:We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology. The ideal candidate will have hands-on experience in SoC and IP-level verification across multiple domains, along with good scripting skills. Exposure to C language is a plus.Key Responsibilities:Develop and execute...

Role Overview:We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology. The ideal candidate will have hands-on experience in SoC and IP-level verification across multiple domains, along with good scripting skills. Exposure to C language is a plus.Key Responsibilities:Develop and execute...

Role Overview:We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology. The ideal candidate will have hands-on experience in SoC and IP-level verification across multiple domains, along with good scripting skills. Exposure to C language is a plus.Key Responsibilities:Develop and execute...

Role Overview:We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology. The ideal candidate will have hands-on experience in So C and IP-level verification across multiple domains, along with good scripting skills. Exposure to C language is a plus.Key Responsibilities:Develop and execute...

Role Overview:We are looking for Senior ASIC Design Verification Engineers with strong expertise in System Verilog (SV) and UVM methodology. The ideal candidate will have hands-on experience in SoC and IP-level verification across multiple domains, along with good scripting skills. Exposure to C language is a plus.Key Responsibilities:Develop and execute...

VeriFast Technologies is expanding and hiring Sr Verification Engineers in Ahmedabad with minimum 7 years of experience with PCIe/PCI-E or UCIe or CXL or RISC-V with strong SV, UVM and hands on AXI and AHB/APB . Do call me at or drop your CV over to