Senior Engineer, Design Verification Engineering

5 days ago


Hyderabad, India BrainChip Full time

This is a full-time role for a Senior Design Verification Engineer for Brainchip’s Hyderabad, India Office. Key tasks include debugging, ensuring designs meet customer requirements, documenting verification plans, and collaborating with cross-functional teams to improve the verification process. Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies. Expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. B.Tech/M.Tech. with 5-10 years of relevant experience. Experience in verification of complex IPs/units and sub-systems. Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies. Knowledge in System Verilog or similar hardware verification language. Experience with System Verilog Assertion (SVA) a plus. Experience with Perl, Python or other scripting language is a plus Experience with Industry Standard protocols like I2C/SPI/GPIO/AXI/APB/AHB is a plus



  • Hyderabad, India ACL Digital Full time

    Senior Design Verification Engineer Looking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging.Should be an enthusiastic and a quick learner of the verification flow.Job Description:SV / UVM Test bench development and test cases codingCode and Functional coverage analysis...


  • Hyderabad, India ACL Digital Full time

    Senior Design Verification Engineer - Looking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging. - Should be an enthusiastic and a quick learner of the verification flow. Job Description: - SV / UVM Test bench development and test cases coding - Code and Functional...


  • Hyderabad, India ACL Digital Full time

    Senior Design Verification Engineer Looking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging. Should be an enthusiastic and a quick learner of the verification flow. Job Description: SV / UVM Test bench development and test cases coding Code and Functional coverage...


  • Hyderabad, India ACL Digital Full time

    Senior Design Verification Engineer- Looking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging.- Should be an enthusiastic and a quick learner of the verification flow.Job Description:- SV / UVM Test bench development and test cases coding- Code and Functional coverage...


  • Hyderabad, India ACL Digital Full time

    Senior Design Verification EngineerLooking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging.Should be an enthusiastic and a quick learner of the verification flow.Job Description:SV / UVM Test bench development and test cases codingCode and Functional coverage analysis...


  • Hyderabad, India ACL Digital Full time

    Senior Design Verification EngineerLooking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging.Should be an enthusiastic and a quick learner of the verification flow.Job Description:SV / UVM Test bench development and test cases codingCode and Functional coverage analysis...


  • Hyderabad, India ACL Digital Full time

    SSOC Design Verification Engineer - Senior / Lead / Sr. Experience: 5 to 12 Years Experience of working in complex test-bench/model in Verilog, System Verilog or System C. Experience of working on Functional Verification, So C Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language OVM/UVM...


  • Hyderabad, India ACL Digital Full time

    Senior Design Verification Engineer Looking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging.Should be an enthusiastic and a quick learner of the verification flow.Job Description:SV / UVM Test bench development and test cases codingCode and Functional coverage analysis...


  • Hyderabad, India ACL Digital Full time

    Senior Design Verification Engineer Looking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging. Should be an enthusiastic and a quick learner of the verification flow. Job Description: SV / UVM Test bench development and test cases coding Code and Functional coverage...


  • Hyderabad, India ACL Digital Full time

    SSOC Design Verification Engineer - Senior / Lead / Sr. Experience: 5 to 12 Years Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC. Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language...