Design and verification Engineer
1 week ago
Experience: 5 years+
Notice Period: Immediate to 30 days
1. Must have strong knowledge in PCIe Gen1/3/4/5 (Logical PHY, LTSSM, DLL & TL)
2. Must have hands-on debugging skills with both log files and waveform. Prior experience on 3rd party test suite is added advantage.
3. Must have SV knowledge like writing Constraints, Assertions, Functional coverage etc.
4. Capable of understanding complex Test benches in a given time.
5. Good to have RAL understanding
Please share your profile to for further discussion.
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