Design Engineer Administrator

1 day ago

Hyderabad, India Silicon Labs Full time
Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. This position involves the development of complex SoC/chip architectures with multi-core, multi-threaded processor subsystems, AI accelerators, interconnects, memory architecture and multi-level caches, multiple clocks and resets, high-speed interfaces, peripherals. The chosen candidate would need to contribute to, and manage a team for, the development of architecture, microarchitecture, and design of SoCs which include RISC-V, ARM or proprietary processor designs, and high-speed interfaces for off-chip memories, along with the integration of wireless systems, power management, and mixed signal IP. The candidate would be responsible for the leading a project through the entire product development process.

Definition and Planning
Provide the necessary design collateral to support the product approval gates.
Develop the design schedule, including milestones and resource requirements. Coordinate with cross functional teams (such as software) on dependencies.
Project Execution
Coordinate with global design functional leads (RF, baseband, verification, etc) to track execution, triage issues, and perform prudent escalation.
Represent the design community to provide succinct weekly status and attend the cross functional meeting. Drive design action items to closure.
Perform SoC Design Integration and maintain design collateral such as documentation, register libraries, and pinouts delivered to cross functional teams.
Follow established quality procedures and processes to achieve first tapeout.
Actively support the validation and product test teams during silicon bringup, validation, characterization, and qualification.
Execute a metal or full layer revision, if necessary

Experience Level: 12+ years in Industry
Bachelor or Master’s degree in Electrical or Computer Engineering

Capable of leading complex IP, SOC development projects execution. Experience coordinating with contractors a plus.
Top-down planning and execution of SOC projects.
Experience in full-chip development cycle
Hands-on experience in architecture, micro-architecture, digital design processes
Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure
Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
Knowledge of scripting languages like Perl, Python, Tcl, shell

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.
Employee Stock Purchase Plan (ESPP)
National Pension Scheme (NPS)
Flexible work policy
Childcare support

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