Renesas Electronics | Sr Mask design Engineer | delhi

2 weeks ago

delhi, India Renesas Electronics Full time
Job Description
Looking for an experienced Layout Design Engineer to join the 2.6B$ Power Business Unit where in the candidate will get to work on a wide range of exciting products such as IPD’s, PMICs, DC-DC converters and Drivers powering the next generation of automotive power needs. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.
Essential Functions:
Experienced in all aspects of Analog layout design from block level to full chip with a demonstrated history in driving design innovation and best practices.
Should have the ability to work independently with little supervision to floorplan and layout typical analog circuits such as charge pumps, comparators, amplifiers, bandgaps, linear regulators etc take complete ownership to drive all aspects within the committed schedule.
Can manage a small group of engineers with a proven history of mentoring new college graduates.
Must have deep knowledge in floor planning, leaf cell layout and analog layout matching techniques along with designing for EM and reliability.
Must be a natural team player and strive towards fostering a highly creative and productive working environment.
Qualifications
Minimum Requirements:
Bachelor’s or master’s degree in electrical and computer engineering
6-10 years in Analog Layout Design and associated flows for DRC, LVS, Packaging
Additional Preferred Qualifications
Solid understanding of IC processing (preferably BCD nodes), packaging and production test along with familiarity with advanced IC CAD tools
SKILL coding and proficiency in any of the scripting languages such as Python, Perl, TCL etc
Expertise in the required CAD tools (Virtuoso XL / Calibre DRC, LVS & PEX / PVS / R3D)
Work closely in collaboration with colleagues in design and layout to minimize need for rework.
Follow methodology guidelines to ensure easy portability of IP across designs.

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