UST | Senior DFT Engineer | bangalore

4 weeks ago


bangalore, India UST Full time

Job Description: Senior DFT Engineer

Number of Positions : 2

Experience : 5 to 8 years

Skillset : ATPG / Verification

Location- Malaysia/ Bangalore/ Hyderabad


We are seeking a Senior DFT Engineer with a strong background in Design for Test (DFT) and hands-on expertise in Automatic Test Pattern Generation (ATPG) and verification processes.


Key Responsibilities :

  • Perform ATPG for Stuck-At Faults (SAF) , Transition Delay Faults (TDF) , and Bridging Faults using industry-standard tools.
  • Execute DFT DRC Analysis , Coverage Analysis , and provide optimization suggestions for test coverage improvements.
  • Conduct Gate Level Simulations (GLS) , including Zero-Delay Simulations and SDF-annotated Timing Simulations .
  • Analyze and debug simulation failures efficiently to identify and resolve root causes, especially in timing-related issues.
  • Ensure robust DFT implementations and verification workflows to meet industry standards and project requirements.


Skills & Expertise :

  • Proficiency with Synopsys ATPG Tool for fault modeling and coverage analysis.
  • Hands-on experience with Cadence Simulator (Xcelium) for test verification and simulations.
  • Strong debugging skills for simulation issues and timing-related failures.
  • In-depth knowledge of GLS verification, timing models, and annotated simulations.
  • Experience in handling large designs and optimizing test insertion flows.


Preferred Skills :

  • Expertise in GLS Verification , with a focus on zero-delay and SDF timing simulations.
  • Familiarity with advanced DFT architectures and methodologies.
  • Good communication and collaboration skills to work with cross-functional teams.


This is an excellent opportunity for experienced DFT engineers to work on cutting-edge designs and be part of a dynamic team. If you meet the criteria, we encourage you to apply



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