Senior principal dft engineer

3 weeks ago

Bangalore, India Mulya Technologies Full time
Senior Principal / Principal DFT Engineer – Bangalore, India Description Our main business focuses on automotive microcontrollers and So Cs.
The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips.
we will continue to integrate the latest electronic and electrical architecture (E/EA) designs from automakers, realize the demands of the next-generation software-defined vehicle, and apply a chip design-oriented, human-centric service-oriented architecture (SOA) to the automotive field.
This approach aims to meet the diverse needs of users and provide consumers with a new user experience.
We are seeking a Lead DFT Engineer for the R&D team based out of our Bangalore, India Office.
This position is a hands-on technical position , working closely with the customer, design, and implementation teams.
Primary Responsibilities: Support and work closely with automotive customers (with special emphasis on in-system test using LBIST & MBIST) and non-automotive customers in defining DFT requirements and specifications for the ASIC Development and Implementation of DFT Architecture Design and Verification of DFT logic and components Generation of structural test vectors, analysis, and coverage improvement Generation of timing constraints for the various DFT modes Work with implementation teams on DFT STA, logical, physical, and power issues Support ATE team with test vector porting, diagnosis, and physical failure analysis Necessary Qualifications: BE/ME, BTech/MTech in Electrical Engineering, Computer Science, or related field Minimum of 12-18 years hands-on work experience in ASIC DFT design.
Experience in an So C product development organization or in an ASIC vendor company along with customer facing experience preferable Hands-on experience with DFT circuit insertion and validation for scan, at-speed, MBIST and Boundary scan Experience with Industry standard DFT/ATPG EDA tools like Tessent/Test Max/Modus.
Experience with simulators and waveform debug tools.
Strong knowledge of DFT methodologies, industrial standards, and practices Strong working knowledge of Chip design, Verilog/System Verilog, and design verification Experience with STA tools like Primetime, SDF generation and Gate-level simulations Understanding and expert handling of Verilog HDL based Netlists, design libraries and Scripting (Perl/Tcl) Contact: Uday Mulya Technologies "Mining The Knowledge Community"

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