Principal Verification Engineer

2 weeks ago

Bangalore, India NXP Semiconductors Full time

Responsibilities: Experience: 10+ years The Principal Verification Engineer is responsible for defining Design Verification strategy, planning and implementing it for an IP, sub-system, or IC level. Objectives & Deliverables: • You will be responsible for the pre-silicon verification of digital IP modules, IP subsystems, and/or the SoC top-level for highly secure microcontrollers: • Take ownership of submodules, subsystems and top-level testbenches. • Track and document the whole verification activity. • Own the subsystem top-level verification documentation including reviews. • Drive the methodology updates and improvements of the whole DV team. • Keep yourself updated with the latest verification methodology and tools. • Interface to HW and SW design teams, as well as to architecture and system teams, to understand the functionality and application of the IP module / SOC / system. • Develop, debug, and modify the test environment for different platforms (RTL, Emulation, FPGA, silicon). • Define the verification strategy for specific IP modules. • Define and code test cases and debug these on the design models (RTL, Power-aware RTL, Gate Level, FPGA, Emulation platform) and on silicon. • Define goals for the verification coverage, implement appropriate methods to measure the verification coverage, and enhance the test cases until coverage goals are met. • Interface to validation and product engineering teams for silicon correlation and debug. Required Skills • Degree in Electrical Engineering or Computer Science, with 8+ years of experience on SOC/Chip level/Sub-System Verification • Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC. • Experience in Microcontroller and Microprocessor architecture, RISC Cores, Interconnect, Cache Coherency. • Experience in protocols like AHB/AMBA, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. • Advanced knowledge of Verilog and System Verilog languages (VHDL is a plus). • High proficiency in Metric Driven Verification concepts, functional and code coverage. • High proficiency in directed and constrained random methodologies. • Good knowledge of formal verification methodologies and assertions. • Experience in setup and execution of Gate Level Netlist simulation with back-annotated timing. • Understanding of software development for embedded CPUs, and experience in developing and debugging software. • Experience with debugging of designs pre- and post-silicon, in simulation and on the bench. • Experience with smart card architectures or security controllers would be a plus.

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