Digital Test Architect
2 weeks ago
About the Role
We are seeking a seasoned Design-for-Test engineer with 3-5 years of experience in ASIC design and verification to enhance our team's capabilities. The ideal candidate will have a strong focus on implementing Design-for-Test methodologies.
Main Responsibilities:
- Develop and implement DFT architectures, including scan insertion, ATPG, MBIST, and boundary scan.
- Work on RTL design modifications for DFT features.
- Generate and validate test vectors using tools like Tetramax/Fastscan.
- Run gate-level simulations and debug test coverage issues.
- Perform pattern validation on emulation/silicon platforms.
- Collaborate with RTL, PD, and validation teams for seamless DFT integration.
Essential Skills:
- Strong knowledge of DFT concepts: scan, compression, boundary scan, ATPG, BIST (LBIST/MBIST).
- Experience with tools such as Synopsys DFT Compiler, Tetramax, Mentor Tessent.
- Scripting skills in Python, Perl, or TCL for automation.
- Familiarity with STA, synthesis, and timing constraints.
- Good understanding of RTL-to-GDS flow.
Why Choose Us?
Acl Digital is a leader in digital engineering and transformation, part of the Altten Group. We empower organizations to thrive in an AI-first world by seamlessly integrating AI and data-driven solutions from Chip to cloud.
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