Senior Test Development Engineer

10 hours ago

Kozhikode, Kerala, India beBeeTest Full time ₹ 1,50,00,000 - ₹ 2,50,00,000
Job Opportunity:

Job Title:

Senior Test Development Engineer

Experience:

7+ Years

Location:

Kozhikode, India

Employment Type:

Full-time

Industry:

Semiconductors / ASIC / SoC Design

Job Description:

We are seeking a Senior Test Development Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.

Key Responsibilities:
  • Develop and Implement DFT Strategies: Develop and implement DFT strategies for multiple ASIC/SoC projects.
  • Implement and Verify DFT Features:
    • Scan insertion and compression (e.g., EDT)
    • ATPG pattern generation and fault grading
    • MBIST and Logic BIST insertion and validation
    • Boundary scan (IEEE 1149.1/1149.6), IJTAG (1687)
  • Manage End-to-End DFT Flow: Oversee the entire DFT process from RTL to gate-level netlist and silicon bring-up.
  • Collaborate with Cross-Functional Teams: Work closely with RTL, STA, PD, and test engineering teams for seamless integration.
  • Perform Pattern Generation, Fault Simulation, and Debug Test Coverage Gaps: Create patterns, simulate faults, and identify areas for improvement.
  • Own DFT Signoff, Timing Closure (DFT-related Paths), and ATE Pattern Delivery: Ensure DFT signoff, timing closure, and delivery of test patterns.
  • Support Silicon Bring-Up, Test Vector Validation on ATE, and Yield Optimization: Assist in silicon bring-up, test vector validation, and yield optimization.
  • Mentor and Guide Junior DFT Engineers: Provide guidance and training to junior DFT engineers.
  • Develop and Maintain DFT Automation Scripts and Infrastructure: Create and maintain automation scripts and infrastructure for DFT.
Required Skills and Qualifications:
  • Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX; Siemens EDA: Tessent ScanPro, MBIST, IJTAG; Cadence/others: Modus, Encounter Test.
  • Strong knowledge of RTL design, STA, and synthesis flows.
  • Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
  • Deep understanding of silicon test challenges and test coverage improvement.
  • Strong leadership, team collaboration, and communication skills.
Preferred Qualifications:
  • Experience with hierarchical DFT and low-power DFT methodologies (UPF).
  • Exposure to post-silicon validation and failure analysis.
  • Familiarity with safety-critical designs (ISO 26262) and functional safety.
  • Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).

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