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Lead DFT Architect
1 week ago
We are seeking an experienced DFT Engineer with 12-20 years of industry experience in the VLSI domain to join our dynamic team at L&T Semiconductor Technologies.
About the Role- Develop and implement DFT architectures and methodologies for advanced SoC designs, focusing on achieving high test coverage and minimizing test time.
- Drive DFT strategy and planning for new projects, collaborating closely with design, verification, and physical design teams to ensure seamless integration of DFT solutions into the overall design flow.
L&T Semiconductor Technologies is a leading player in the semiconductor industry. We offer a collaborative and dynamic work environment that fosters growth and innovation.
ResponsibilitiesDFT Implementation- Lead DFT implementation activities including scan insertion, ATPG (Automatic Test Pattern Generation), BIST (Built-In Self-Test), and boundary scan (JTAG) insertion.
- Perform DFT verification and sign-off, including scan chain simulations, stuck-at and transition fault simulations, and DFT coverage analysis.
- Work closely with Test Engineering Team to ensure successful manufacturing test bring-up and production test program development.
- Investigate and resolve DFT-related issues encountered during silicon bring-up and production testing, collaborating with cross-functional teams to implement effective solutions.
- 12-20 years of industry experience in DFT engineering, with a proven track record of delivering successful DFT solutions for complex SoC designs.
- Proficiency in industry-standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test.
- Strong expertise in DFT architectures, methodologies, and techniques, including scan insertion, ATPG algorithms, BIST Architectures, and JTAG.
- Master's degree in Electronics engineering, Electrical Engineering, Computer Engineering, or related field.