Senior Design Verification Specialist
4 days ago
We are seeking an experienced and skilled Senior Design Verification Engineer to join our verification team.
The ideal candidate will have a deep understanding of the verification lifecycle, from test planning to coverage closure, and be able to drive complex verification tasks for IP, subsystem, or full-chip level designs.
Key Responsibilities:- Develop and execute test plans for IP/subsystem/full-chip level verification.
- Build and maintain constrained-random and directed testbenches using SystemVerilog and UVM.
- Drive functional coverage closure and ensure high-quality tape-outs.
- Collaborate with RTL designers, architecture, and software teams to understand design features and define test scenarios.
- Participate in code reviews, debug RTL/testbench issues, and file bug reports.
- Use industry-standard tools like VCS, QuestaSim, Verdi, Synopsys, Cadence, or Mentor toolchains.
- Mentor junior team members and lead small verification teams or projects when required.
- Support post-silicon validation teams and participate in bring-up/debug if necessary.
As a highly skilled verification engineer, you will play a key role in ensuring the quality and reliability of our products. If you are passionate about verification and have a strong background in engineering, we encourage you to apply for this exciting opportunity.
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