Senior ASIC Design Engineer Position Open at Mulya Technologies
5 hours ago
Mulya Technologies is seeking a highly skilled Principal IP Design Engineer to join our team. As a key member of our design team, you will be responsible for creating micro-architecture and detailed design documents, performing RTL coding, and working closely with the verification and back-end teams.
Responsibilities:
• Creating micro-architecture and detailed design documents for design keeping in mind performance, power, area requirements.
• Performing RTL coding for complex design blocks in Verilog.
• Function/performance simulation check and debug.
• Understanding on Lint/CDC/Synthesis checks, power analysis and LEC check.
• Understanding and defining constraints.
• Issue and track bug reports from beginning to closure.
• Work with the team to deliver quality designs.
Key Qualifications:
• B.E/M. Tech with 8-12 years of experience in ASIC RTL development.
• Solid experience with System Verilog.
• Experience with Lint, CDC.
Why Work with Us:
Mulya Technologies is a well-funded product-based startup with design centers established in strategic locations. We offer a dynamic and collaborative work environment that fosters growth and innovation.
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