Advanced CPU Physical Design Expert

3 days ago

Bengaluru, Karnataka, India beBeeHighSpeed Full time

Job Title: CPU Physical Design Lead

10+ Years of Experience Required

  • High-Speed Core Development – Synthesis, Constraints, and Physical Design
  • Significant knowledge on high-speed cores including CPU, GPU, DDR etc.
  • Must have synthesis & Constraints experience with PPA in mind
  • Must work with RTL designers for optimizations and feedback
  • Must be knowledgeable on silicon margins, VT trade-off, power and area impact.
  • Floorplanning for multi-core, L2 & L3 and power planning all the way to Bumps.
  • Should have knowledge on critical paths, pipelining, Latency and super buffer implementations etc.
  • Low power implementation knowledge is an added advantage.

About the Role:

7Rays Semiconductors. is a provider of end-to-end custom SoC design solutions ranging from SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. We are focused on providing services to top semiconductor and system companies to help them with the design of their complex SoCs.

We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a strong engineering team and a proven track record of successful project executions, we are committed to excellence and innovation in SoC Design, Development and deployment of customers' products.

Our goal is to provide world-class SoC design solutions that meet the evolving needs of our clients.

Responsibilities:

• High speed core development using synthesis, constraints, and physical design techniques

• Engineer must have significant knowledge on high-speed cores including CPU, GPU, DDR etc

• Must have synthesis & Constraints experience with PPA in mind

• Must work with RTL designers for optimizations and feedback

• Must be knowledgeable on silicon margins, VT trade-off, power and area impact.

• Floorplanning for multi-core, L2 & L3 and power planning all the way to Bumps.

• Should have knowledge on critical paths, pipelining, Latency and super buffer implementations etc.

• Low power implementation knowledge is an added advantage.

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