Senior ASIC SoC Verification Engineer

13 hours ago

Bengaluru, Karnataka, India beBeeVerification Full time US$ 1,00,000 - US$ 1,50,000

Job Title:

Advanced Silicon Design Verification Expert

We are seeking an experienced ASIC SoC verification professional to join our team. The ideal candidate will have a strong background in digital design verification and experience working with complex SoC designs.

Key Responsibilities:

  • Collaborate with cross-functional teams to understand architecture and verification requirements
  • Develop detailed test plans based on architectural specifications
  • Have a good understanding of SoC design and architecture
  • 8 years of design verification experience with strong Verilog, SystemVerilog, C, and UVM/OVM knowledge
  • Candidate should be able to develop testbenches and thorough understanding of verification environments including stimulus, checkers, scoreboards, coverage aspects, and developing functional coverage assertions
  • Own the DV sign-off and ensure a bug-free design
  • Work with the post-silicon team on debug support and help root-cause any failures
  • Have worked on wireless protocol design verification
  • Bringing up testbench/SoC verification environment and good understanding of SoC RESET/CLOCK flow
  • Exposure to DEBUG concepts such as JTAG etc
  • Comfortable with VCS/Verdi and excellent debug skills
  • Logical in thinking and ability to gel well within a team
  • Good communication skills
  • Continuously drive methodology improvements to improve efficiency
  • Mentor junior engineers to build a high-performing team

Preferred Experience:

  • Proficient in SoC/sub-system/IP level ASIC verification
  • Proficient in debugging firmware and RTL code using simulation tools
  • Proficient in using UVM testbenches
  • Experienced with Verilog, SystemVerilog, C, and C++
  • Worked on any High Speed Interface like PCIE/DDR/USB/Other and good understanding of AXI/AHB/APB Bus protocol
  • Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification
  • Developing UVM-based verification frameworks and testbenches, processes, and flows
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
  • Scripting language experience: Perl, Python, Makefile, shell preferred

Why Join Our Team?

As a member of our team, you will have the opportunity to work on complex and challenging projects, collaborate with experienced professionals, and grow your skills and expertise. We offer a dynamic and supportive work environment that values innovation, teamwork, and continuous improvement.

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