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System Verification Specialist

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System Verification Specialist

We are seeking a skilled System Verification Specialist to execute system-level performance verification, traffic patterns, bandwidth & latency analysis using System Verilog based UVM Functional verification.

Key Responsibilities:

  • Develop and execute testbenches to validate the functionality and correctness of models
  • Participate in system-level testing and debugging
  • Setup verification environment and bring up simulations with various simulators such as VCS / Questa / Xcellium / Riviera
  • Expertise in AXI4 bus protocol, Network On Chip (NOC) protocol, and multi-master, multi-slave AXI4 use-case configurations
  • Knowledge of DRAM memory controllers and Vivado for simulation debugs

Requirements:

  • 5-7 years of experience in system level performance verification
  • Expertise in System Verilog based UVM Functional verification
  • Knowledge of AXI4 bus protocol, Network On Chip (NOC) protocol, and multi-master, multi-slave AXI4 use-case configurations
  • Experience with DRAM memory controllers and Vivado for simulation debugs

Deliverables:

  • Validated and functional models
  • System-level testing and debugging reports
  • Simulation setup and bring-up documentation