Leading Digital Design Expert
2 weeks ago
We are seeking talented professionals to join our team in the role of RTL Design Engineer and Design Verification Engineer.
As an ideal candidate, you should have a strong background in digital design and verification. Experience with tools like Lint, CDC, Synthesis, and Spyglass is highly desirable. Additionally, knowledge of AMBA protocols, including AXI, AHB, APB, and SoC clocking/reset architecture, would be beneficial.
For the RTL ASIC engineer position, we require 7+ years of experience in ASIC/IP Design, Logic design/Rtl design, and IP design integration. Proficiency in using tools for ASIC development, such as Lint and CDC, is essential. Knowledge of synthesis/timing concepts and familiarity with good coding practices are also plus factors.
In the design verification engineer role, you will be responsible for verifying complex IP blocks and SoCs. To excel in this position, you should have 5-20 years of experience in SV/UVM-based IP verification, SOC verification using C/SV, and third-party VIP integration. Additional skills in interconnect protocols (AHB, AXI, APB), SOC interfaces (GPIO, SPI, I2C, UART), high-speed serial interfaces (PCIe Gen 3/4, USB, MIPI), memory interfaces (DDR, HBM I/O), coverage closure, and technical documentation are highly valued.
If you are passionate about digital design and verification, and possess the necessary skills and qualifications, please submit your updated cv to gayatri.kushe@tessolve.com or connect on 6361542656.
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