
Memory Compiler Layout Specialist
20 hours ago
Role Overview:
The Memory Compiler Layout Specialist will be responsible for developing high-quality memory compilers layouts and creating memory Fast Cache instances layouts to achieve outstanding Performance, Power, and Area (PPA) in next-generation Cores.
Key Responsibilities:
- Developing advanced memory compilers layouts.
- Creating efficient memory Fast Cache instances layouts.
- Achieving exceptional PPA in next-generation Cores.
Requirements:
- Hold a graduate or postgraduate degree in Electronic Engineering or equivalent engineering degree from a University or Engineering School.
- Basic understanding of CMOS Transistors and their behaviors.
- Understanding of CMOS logic design and layout principles.
- Knowledge of Power versus Performance versus Area trade-offs in typical CMOS design.
- Excellent interpersonal skills and engineering demeanor.
- Ability to create high-quality design rule-driven layouts.
- Capacity to review schematics with engineering teams and propose changes based on layout implications.
- Exploring possible floor planning options and proposing improvements.
- Minimum 5 years of experience in SRAM/memory layouts creation and backend verifications including EMIR analysis.
Nice to Have Skills and Experience:
- Basic programming languages, e.g., Perl/Python.
- Experience working on Cadence or Synopsys flows.
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