Digital Signal Processing Manager
6 days ago
About InnoPhase Inc., DBA GreenWave Radios
We are a cutting-edge innovation company at the forefront of Open RAN digital radios. Our solutions, powered by the Hermes64 RF SoC, aim to enhance network energy efficiency while reducing operational expenses.
As a pioneer in power-efficient digital-to-RF technology, we have earned a reputation for delivering high-quality solutions. With over 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of patent filings, we continue to push the boundaries of radio technology.
InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. This arrangement enables us to focus on developing innovative SOC cellular radio integrated circuit products while providing our employees with the best benefits and services.
Job Summary
We are seeking a Digital Signal Processing Manager to join our growing start-up semiconductor development organization. As a key member of our team, you will be responsible for driving excellence in our 5G ORAN products.
Key Responsibilities:
- Manage a team of 3-4 Design Engineers for technical leadership and mentoring team members for career growth.
- Work as primary interface to US design/verification members and management team.
- Provide executive summary on project tracking, identify and close gaps for design status.
- Contribute to 5G cellular product specifications and architectures.
- Architect and RTL design on CPU & bus system integration, SERDES PCS/PMA control, Rx/Tx signal processing.
- Participate in design verification to achieve cycle true and bit accurate matching with fix point model.
- Running CDC, LINT, LEC tools for RTL designs.
- Create design constraint file for synthesis.
- Work with PD team for timing closure.
- Collaborate with System, Software, RF, Analog, and Test teams and provide necessary support.
Requirements:
- M.Tech/PhD EE/CS preferred.
- 15 years or more years of experience mixed-signal SoC development required.
- 5+ years of project and team management experience with track record of silicon tape out.
- Hands-on RTL design experiences with Verilog/System Verilog focusing on signal processing HW design such as FIR filter, AGC, FFT/IFFT & etc.
- Thorough understanding of AMBA (AXI, AHB, APB) bus protocol and design requirements.
- Experience on multi-core CPU system and peripheral integration.
- Experience of front-end tools (Verilog simulators, linters, clock-domain crossing checkers).
- Experience in gate level simulation and LEC checking.
- Experience using logic synthesis tools from RTL release to gate level synthesis.
- Experience in static timing analysis, defining timing constraints and exceptions, corners/voltage definitions.
- Experience bringing highly integrated mixed signal SoCs to commercial mass production.
- Experience with embedded systems, wireless protocols, power management, signal processing and standard digital interfaces.
- Strong background in digital communication architecture.
- Team player with strong sense of urgency to complete projects on time.
- Strong communication and presentation skills.
- Good skills and interest in mentorship.
Estimated Salary: $150,000 - $200,000 per annum
Benefits:
- Competitive salary and stock options.
- Learning and development opportunities.
- Employer paid health Insurance.
- Earned, Casual, Sick & parental leaves.
Contact Information:
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