Digital Verification Expert
22 hours ago
About the Role:
We are seeking a seasoned Digital Verification Engineer to join our team at LeadSoc Technologies Pvt Ltd. The ideal candidate will have a strong background in digital design verification, with expertise in SystemVerilog and UVM.
Key Responsibilities:
- Verify complex SoCs, IP blocks, or custom logic designs using SystemVerilog and UVM.
- Develop high-quality verification code, including UVM sequences, drivers, and scoreboards.
- Analyze waveforms and logs to identify and resolve issues.
- Familiarity with FPGA or ASIC design and verification flows is preferred.
Requirements:
- 5+ years of experience in digital design verification.
- Deep knowledge of SystemVerilog for functional verification.
- Expertise in creating UVM-based verification environments.
- Solid understanding of verification methodologies, coverage metrics, and assertion-based verification.
Preferred Skills:
- Experience with advanced verification techniques, such as formal verification or low-power design verification.
What We Offer:
- A competitive salary range: $120,000 - $180,000 per annum, depending on location.
- A dynamic work environment with opportunities for growth and professional development.
- A comprehensive benefits package, including health insurance, retirement plan, and paid time off.
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