Silicon Design Lead
7 days ago
At Advanced Micro Devices, we're driven by a passion to push the boundaries of innovation. As a leading technology company, we're committed to enriching our industry, communities, and the world through cutting-edge products that accelerate next-generation computing experiences.
A Culture of Excellence
Our mission is to build great products that drive transformation. Underpinning this mission is our culture, which embodies execution excellence, directness, humility, collaboration, and inclusivity of diverse perspectives. We strive for innovation to solve the world's most pressing challenges, and we believe in empowering our teams to deliver high-quality results on schedule.
The Role
The scoping of SOC PD FEINT lead includes Synthesis, Logic Equivalence, low power check, Timing Closure, and full-chip SDC constraints generation. AMD design is big and complex, with advanced process and technology. The FEINT lead needs to have rich experience in each domain, control execution risk, and lead the team to do high-quality releases on schedule. The lead must co-work with IP DFT PD teams, highlighting critical issues, and making decisions to ensure smooth project execution.
The Person
* 13 years working experience on ASIC Implementation
* Knowledgeable in all aspects of ASIC design flow
* Familiar with FEINT EDA tools
* Good leadership skills
* Good teamwork and script skills
* Good training skills to ramp-up new team members
Key Responsibilities
- Own full-chip, sub-system, partition level Synthesis, Equivalence checking and low power checks signoff
- Co-work with IP DFT PD team to improve timing area power during synthesize
- Netlist quality check including EQV LowPower Timing
- Generate full-chip level SDC and SDC quality check
- Do working assignment for team members, tracking and supporting for critical problems
- Own end-to-end delivery of designs, SOC and Sub-system integration from timing constraints and timing signoff perspective
- Understand timing margins, LVF, SSTA Variations etc on the latest tech nodes and work with timing methodology teams for future and current projects
- Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology
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