Senior ASIC Design Verification Specialist
4 weeks ago
We are seeking a highly skilled Design Verification Engineer to join our team at UST. As a key member of our ASIC design verification team, you will be responsible for ensuring the quality and reliability of our complex System IP features.
Key Responsibilities- Develop and execute test plans and validation vectors to ensure functional completeness of our ASIC designs.
- Collaborate with RTL designers and SOC teams to scope out integration and verification requirements.
- Design and implement test benches and monitors for the Design Under Test (DUT).
- Develop C/C++/UVM models for simulation and verification.
- 4+ years of experience in the ASIC design and verification industry.
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
- Strong knowledge of industry-standard integration flows and design for verification techniques.
- Experience with VCS simulation tools, Perl/Shell scripting, and Verilog RTL design.
- Familiarity with Linux environment and high-level verification flows such as SV, UVM, C++.
- Experience with assertion-based design strategies, code coverage, functional coverage, and test plans.
- Knowledge of industry-standard tools for verification and gate-level simulation.
- Ability to work in a fast-paced environment and collaborate with cross-functional teams.
We offer a competitive salary and benefits package, including health insurance and a collaborative work environment.
Contact Ms. Van Anh for more information.
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