Verification Expert
20 hours ago
Job Title: Verification Strategy Lead
About the Role:
We are seeking a seasoned Verification Strategy Lead with extensive expertise in ASIC/SoC Design Verification to drive critical projects forward.
Key Responsibilities:
- Lead technical leadership, project execution, and team management within the Design Verification domain.
- Define verification strategies, test plans, coverage goals, and closure metrics in alignment with industry standards.
- Provide technical guidance in SystemVerilog, UVM-based testbench development, coverage closure, debugging, and verification methodologies.
- Collaborate with architects, designers, and DV engineers across global teams to ensure seamless execution.
- Manage multi-site DV teams, track progress, and mitigate risks through proactive planning.
- Conduct status reporting, milestone reviews, and stakeholder interactions.
- Mentor junior engineers and ensure adherence to best practices in verification and project management.
- Drive continuous improvements in automation, regression efficiency, and verification productivity.
Required Skills & Experience:
- 14 to 20+ years of experience in Design Verification (IP / Subsystem / SoC level).
- Strong expertise in SystemVerilog, UVM, SVA, and coverage-driven verification.
- Hands-on knowledge of AMBA protocols (AXI, AHB, APB) and Memory/DRAM verification flows.
- Experience with Gate Level Simulation (GLS), Low Power (UPF), and Formal Verification is a strong plus.
- Exposure to EDA tools such as Cadence Xcelium, Synopsys VCS, and Verdi.
- Proven experience in project/program management, leading DV teams (10+ engineers).
- Strong stakeholder management, planning, and execution skills.
- Excellent communication and leadership skills.
What We Offer:
- Opportunity to work on cutting-edge projects.
- Chance to develop technical expertise in verification methodologies.
- Collaborative environment with experienced professionals.
- Professional growth and development opportunities.
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