CPU Architectural Designer Leader

2 days ago


Kozhikode, Kerala, India beBeeInterconnect Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Job Title: CPU Architecture and Logic Design Lead

The ideal candidate will be responsible for the development of high-bandwidth, low-latency on-chip interconnects (NoC) and chip-to-chip interconnects.

Key Responsibilities:

  • Design and architect different interconnect topologies as driven by bandwidth, latency, and RAS requirements
  • Develop the features and present proposed architectures in high-level design discussions
  • Collaborate with verification, DFT, physical design, FW, SW teams to develop features
  • Ensure pre-silicon designs meet all functional, area, and timing goals
  • Participate in silicon bring-up and validation of hardware

Required Education:

Masters Degree in relevant field

Desired Skills and Qualifications:

  • At least 1 generation of processor interconnect design delivery leadership
  • Expertise in SMP coherency
  • Experience in different on-chip interconnect topologies
  • Understanding of various snoop and data network protocols
  • Understanding of latency & bandwidth requirements and effective means of implementation
  • Working knowledge of queuing theory
  • NUMA/NUCA architecture
  • Proficient in HDLs - VHDL / Verilog
  • Experience in High speed and Power efficient logic design
  • Good understanding of Physical Design and collaboration with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design
  • Experience in leading uarch, RTL design teams for feature enhancements


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