
Unlock Career Opportunities as a DFT Expert
17 hours ago
Job Overview:
- Develop and implement Digital Fault Tolerance (DFT) architecture with a focus on Memory BIST for advanced System-on-Chips (SoCs).
- Integrate BIST Intellectual Property (IP), generate test insertion and verification infrastructure.
- Work on DFT planning, insertion, simulation, and pattern generation.
- Perform Automatic Test Pattern Generation (ATPG) and BIST pattern generation and debug failures from silicon bring-up.
- Collaborate with RTL, Physical Design, and Verification teams throughout the design cycle.
- Support silicon bring-up and yield improvement activities post-silicon.
- Ensure high coverage and test quality in scan and BIST.
About You:
- Bachelor of Engineering or Master of Engineering degree in Electronics or related field.
- Minimum 7+ years of hands-on experience in DFT with a strong focus on ATPG, SCAN, and BIST.
- Proficient in tools such as Synopsys DFT Compiler, Tessent (Mentor), or equivalent.
- Solid understanding of scan insertion, ATPG, boundary scan, and JTAG.
- Experience with memory test algorithms, repair analysis, and pattern generation.
- Familiarity with scripting languages (TCL, Perl, Python) for automation.
- Strong analytical and problem-solving skills with the ability to work independently.
We're looking for an expert in DFT to join our team
This role offers the opportunity to work with cutting-edge technologies and collaborate with talented engineers. If you're passionate about digital fault tolerance and want to take your career to the next level, apply now
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