DFT Leader

We are seeking an experienced professional to lead our Design for Test (DFT) activities.

The ideal candidate will have extensive knowledge of DFT concepts, as well as hands-on experience in scan insertion, ATPG, coverage analysis, and transition delay test coverage analysis.

In addition, the successful candidate will have expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations, and experience in scripting languages such as perl and shell.

The DFT Lead will be responsible for ensuring that designs meet required quality and reliability standards.

• Expertise in DFT concepts
• Hands-on experience in scan insertion, ATPG, coverage analysis, and transition delay test coverage analysis
• Knowledge in providing timing fixes/corrective actions for timing violations
• Experience in scripting languages such as perl and shell
• Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test
• Excellent problem-solving skills, communication, and teamwork skills