Highly Experienced RTL Design Engineering Professional
4 days ago
A seasoned professional in the field of RTL design engineering is sought after for a challenging position.
As part of our dynamic team, you will be working on the development and optimization of digital circuits at the register-transfer level (RTL) using Verilog. Your primary responsibilities will include designing low-power RTL designs, microarchitectures, and synthesis, as well as ensuring timing closure and performing power estimation.
In this role, you will have the opportunity to work on various projects that involve optimizing microarchitectures and RTL for area and power reduction. This includes designing Arithmetic units and Floating point datapath designs, as well as working with ASIC design tools such as VCS, Verdi, and Design Compiler. Additionally, knowledge of power estimation tools like Spyglass and PTPX, as well as scripting languages like Shell, Perl, and Python, is highly desirable. Experience with hardware architecture exploration and performance modeling will also be considered an asset. Furthermore, prior experience in Machine learning/Artificial Intelligence domain or DRAM Memory controllers can provide an added advantage.
A critical aspect of this position is ensuring that all RTL designs meet the required standards for Lint and CDC. With PCIe/CXL experience being highly valued, we are looking for a skilled engineer who can contribute their expertise to drive project success. If you have a strong background in RTL design engineering and are passionate about delivering high-quality results, we encourage you to apply for this exciting opportunity.
About the Role:
As a Senior RTL Design Engineer, you will be responsible for designing and optimizing digital circuits at the RTL level, utilizing Verilog and other relevant tools. Key areas of focus include:
• Low-power RTL design and microarchitecture
• Synthesis and timing closure
• Power estimation and optimization
• Hardware architecture exploration and performance modeling
• Lint and CDC compliance
Requirements:
To succeed in this role, you should possess:
• 5+ years of experience in RTL design engineering
• Proficiency in Verilog and experience with ASIC design tools
• Knowledge of power estimation tools and scripting languages
• Strong understanding of hardware architecture exploration and performance modeling
• Prior experience in Machine learning/Artificial Intelligence domain or DRAM Memory controllers (desired)
• Excellent problem-solving skills and ability to work under pressure
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