
VLSI Verification Leadership Role
3 days ago
We are seeking an experienced VLSI verification expert to lead and mentor a team of engineers in ensuring the functional verification of full FPGA designs.
The ideal candidate will have a strong background in FPGA or ASIC verification, leadership skills, and hands-on experience in writing System-verilog UVM agents and environments from scratch. Excellent communication and organizational skills are also required. Expertise in simulation tools such as Xcelium, Questasim or VCS is a plus.
Key Responsibilities:- Lead and mentor VLSI verification engineers
- Develop and implement verification plans, strategies, and methodologies
- Collaborate with FPGA designers and system architects to achieve project goals
- Maintain and improve verification environments and agents using System Verilog UVM methodologies
- Monitor and report verification progress, coverage metrics, and quality indicators.
Our organization values technical excellence, innovation, and teamwork. We are looking for a talented and motivated individual to contribute to the success of our projects.
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