Senior Design Verification Specialist

2 days ago

Chennai, Tamil Nadu, India beBeeVerification Full time US$ 1,20,000 - US$ 1,70,000

Job Title: Principal Verification Engineer

We are seeking a skilled and experienced Principal Verification Engineer to join our team.

The successful candidate will be responsible for leading the design verification process, developing verification environment architecture documents, reviewing and revising code to meet agreed-upon acceptance criteria, and performing RTL simulations using Synopsys and Cadence simulators.

  • Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit, Subsystem, and SOC level verification
  • Performing UPF (Unified Power Format) based Power Aware simulations
  • Coding of Assertion and Functional Coverage bins in SVA (System Verilog Assertions)

The ideal candidate will have a strong background in digital design verification, excellent problem-solving skills, and the ability to work effectively in a team environment. If you are a motivated and detail-oriented individual with a passion for verification engineering, we encourage you to apply for this exciting opportunity.

Required Skills and Qualifications:

  • Bachelor's degree in Computer Science, Electrical Engineering, or related field
  • 7+ years of experience in digital design verification
  • Strong understanding of System Verilog, UVM, and C programming languages
  • Experience with Synopsys and Cadence simulators
  • Excellent problem-solving skills and attention to detail

Benefits:

  • Competitive salary and benefits package
  • Ongoing training and professional development opportunities
  • Collaborative and dynamic work environment

Others:

  • Opportunity to work on cutting-edge technology projects
  • Chance to collaborate with a talented team of engineers

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