
RTL Design Expert
15 hours ago
Key Role: Senior RTL Design Engineer
We are seeking a highly skilled RTL Design Engineer to join our team. The ideal candidate will have a strong background in RTL design, with expertise in low power design, microarchitecture, synthesis, timing closure, and low power estimation.
A critical aspect of this role is the ability to design and optimize RTL for area and power reduction. Proficiency in Verilog is essential.
In addition to these key responsibilities, the successful candidate will also have experience with ASIC design tools such as VCS, Verdi, and Design Compiler. Knowledge of power estimation tools and scripting languages (Shell, Perl, Python) is also required.
The role involves hardware architecture exploration and performance modeling, and we are looking for someone with a strong understanding of these areas.
Preferred Qualifications:
- Experience in machine learning/artificial intelligence domain
- DRAM Memory controllers experience
- LINT and CDC experience
- RTL Design experience on PCIe/CXL
Requirements:
- 5+ years of experience in RTL design
- Strong knowledge of Verilog
- Experience with low power estimation and optimization
We offer a dynamic and supportive work environment that fosters growth and innovation.
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