Senior Digital Fault Tolerance Architect

2 weeks ago


Bangalore, India Whitefield Careers Full time

About the Role

We are seeking an experienced Senior Digital Fault Tolerance Architect to lead the design, development, and implementation of complex DFT architectures for our products.

Key Responsibilities

• Develop end-to-end DFT architectures for complex integrated circuits, ensuring high-quality and testability.
• Collaborate with third-party IP providers to integrate their IP into our designs, ensuring seamless compatibility and testability.
• Lead the development and execution of ATPG and MBIST flows, ensuring comprehensive fault coverage.
• Work closely with cross-functional teams (design, verification, manufacturing) to ensure successful DFT implementation and product quality.
• Conduct thorough design verification using Lint, SPYGLASS DFT, and CDC checks at partition and SOC levels.
• Execute timing and no-timing GLS for ATPG, SAF, TDF, IDDQ, SBF, DBF, and persistence faults using Synopsys VCS and NC simulation.
• Utilize DFT_Builder and Collage flow for DFT_RTL design.
• Leverage TCL and Python scripting for automation and efficiency.

Qualifications

• Experience: 3-5 years of experience in DFT architecture and design.
• Technical Skills: Strong experience in end-to-end DFT architecture, third-party IP integration, ATPG, MBIST, design verification tools (Lint, SPYGLASS DFT, CDC), gate-level simulation, and DFT_RTL design.
• Knowledge: Familiarity with 28nm and 65nm technologies.

Benefits

• Competitive salary and benefits package
• Opportunities for professional growth and development
• Collaborative and supportive work environment



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