DFT Engineer
4 weeks ago
**Key Responsibilities:**
• Design and develop DFT architectures for SoC style chips, including multi-clock domain and low power design practices.
• Implement and test Scan, MBIST, and low power design methodologies.
• Collaborate with cross-functional teams to integrate DFT designs into chip-level architecture.
• Develop and maintain ATPG/SCAN/MBIST/JTAG implementation at chip and block level.
**Requirements:**
• 3-15 years of experience in DFT design and development.
• In-depth knowledge of SoC style DFT architectures and low power design practices.
• Strong understanding of DFT simulations and debugging.
• Excellent communication and collaboration skills.
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