
Digital Circuit Validator
6 days ago
Job Title:
We are seeking an experienced Design Verification Engineer to join our team.
The successful candidate will be responsible for designing and implementing verification plans, scripts, and environments to validate the functionality and performance of digital circuits and systems.
The ideal candidate will have a strong understanding of digital design principles, verification methodologies, and tools such as UVM, SystemVerilog, and simulation software.
Required Skills:
- GLS (Gate-Level Simulation) experience with ZD/PAGLS/SDF/Scan dump verification
- Strong Debugging skills with ability to debug Netlist functional failure
- UVM and System Verilog expertise
- Digital Fundamentals knowledge
- Low Power Aware verification
- Timing Simulation failure, setup, and hold violation fundamentals
- Scan Dump Verification
- Understanding Specs and Standards and developing relevant test plans
- Monitors, scoreboards, sequencers, and sequences utilizing scripts, System Verilog, UVM, and methodologies to increase the rate of bug detection and resolution
- Good Understanding of DDR families (LP/PC) and generations (DDR2/3/4/5)
- Bus Protocols like AHB/AXI/ACE/ACE-Lite
Benefits:
This role offers a challenging and rewarding opportunity for a motivated individual to contribute to the success of our organization.
Others:
Please submit your updated resume to janagaradha.n@acldigital.com for consideration.
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