ASIC Design Expert
5 days ago
We are seeking a highly experienced Senior ASIC Physical Design Engineer to lead all aspects of physical design for full-chip and block-level designs.
- Leading all aspects of physical design, including floorplanning, placement, budgeting, clock tree planning and analysis, scan reordering, and routing.
- Collaborating with the methodology team to solve implementation challenges and provide inputs to improve the physical design flow.
- Design automation, timing constraints, SI prevention, power reduction, and prior experience with Synopsys/Cadence/Mentor place and route tools.
- Maintaining strong communication and presentation skills, as well as good interpersonal skills and problem-solving ability.
To succeed in this role, you will need:
- 4+ years of experience in ASIC physical design.
- Experience with block implementation, extraction, timing, and/or full-chip designs.
- Strong communication and hands-on TCL/Perl development skills.
PREFERRED QUALIFICATIONS:
If you have experience as a full-chip floorplanning, routing, or timing lead for a large silicon project and a track record of taping out complex chips on advanced process nodes, we would like to hear from you.
This position requires a high degree of autonomy, excellent problem-solving skills, and the ability to work effectively in a team environment. The successful candidate will be responsible for developing and implementing design methodologies, collaborating with cross-functional teams, and driving process improvements.
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