Senior Verification Specialist
21 hours ago
We are seeking a seasoned Verification Specialist to enhance our engineering capabilities.
This role will be pivotal in the development of comprehensive test plans, coding and deployment of ASM and C++ tests, maintenance and updates of UVM test bench components, debugging and resolution of regression failures, and retention of protocol knowledge.
Responsibilities:
- Developing strategic test plans
- Coding and implementation of assembly language (ASM) and C++ tests
- UVM test bench component design and maintenance
- Regression failure analysis and resolution
- Extensive understanding of protocols including DDR, PCIe, USB, MIPI, and PCIe
Requirements:
- Minimum 4 years of experience in verification engineering
- Proficiency in assembly language, UVM, SystemVerilog (SV), and C++
- Expertise in developing complex test benches/models using UVM, Verilog, and SystemVerilog
- Able to create readable, maintainable, and verifiable code using UVM, SV, and strong digital design concepts
- Added advantages: experience in power management, clock, reset, DPI interface, Ruby/Perl scripting skills
Why Apply:
As a Verification Specialist, you will play a critical role in the development and deployment of innovative solutions. If you have a passion for verification engineering and a desire to contribute to cutting-edge projects, we encourage you to apply.
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