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Senior Physical Design Engineer
1 month ago
Job Description
About the Role
We are seeking a highly skilled Senior Physical Design Engineer to join our team at Infineon Technologies. As a key member of our design team, you will be responsible for planning and executing all aspects of physical design, including synthesis, floor planning, place and route, clock tree synthesis, IP integration, extraction, physical verification, and taking blocks to closure.
Responsibilities
- Responsible for planning and execution of all aspects of physical design, including synthesis, floor planning, place and route, clock tree synthesis, IP integration, extraction, physical verification, and taking blocks to closure.
- Design Application Engineering will be responsible for supporting project teams using Infineon Design System (flows, design package & design assistance).
- First point of contact for project teams in case of issues and work to achieve the highest customer interaction.
- Responsible for automation of manual processes (including design flow/design package qualification mechanisms, generation of test reports/dashboards etc.) and providing automation requirements for reducing manual steps in qualification.
- Candidate will have an internal drive to work with design and EDA vendors to solve issues and adopt new flows.
- Candidate should have reasonable ability to automate design work by means of script programming, Tcl/tk, Perl or Python.
Requirements
- Candidate should have a minimum of 6 years of relevant working experience in physical design implementation areas including synthesis, LEC, and PnR as well as good exposure to signoff areas, particularly power, timing, and IR signoff.
- Candidate should have a deep understanding of and be able to cater to design concerns across semi-custom design flows, including RTL analysis, synthesis, LEC, place and route, STA, EM/IR, and physical verification.
- Candidate should be able to identify flow gaps and provide automation on a need basis to perform all design activities in the most efficient and correct-by-construction way.
- Candidate should be able to evaluate solutions from multiple available options and be able to perform trade-offs between technical features.
- Analyse the results and any inconsistency issues to be reported via bug tracking system.
- Candidate will work with R&D in Infineon globally and EDA tool vendors to resolve issues across semi-custom design flows.
- Candidate will coordinate with IT and EDA tool license teams to provide an infrastructure aligned with project needs.
- Candidate should have exposure to basic version management using any of Clearcase/Perforce/Cliosoft/Git.
- Candidate should possess excellent communication skills to interact effectively with peers and customers in a clear and honest manner with consistent and open to learning new technical areas if the need arises.
- Candidate should define and monitor key test metrics, build regression status reporting dashboard, develop and execute QA test plans, verification methodology & test strategies for digital block/chip level to maximize the coverage of features/methodology supported in the technologies/design flows.
